The present invention relates generally to semiconductor device testing and, more particularly, to a method and apparatus for identifying broken pins in a test socket.
Semiconductor die are normally formed in large quantities on wafers of semiconductor material, for example, silicon. After die are singulated from the wafers, they may be individually packaged in plastic or ceramic packages, for example. A lead frame may support the die for wire bonding and packaging and provide the lead system for the completed package. In general, electrical circuitry formed on the die is coupled to bond pads on the die to facilitate interconnection of the electrical circuitry with the outside world. During the wire bonding and packaging process, each bond pad is electrically connected by way of wire leads to the lead frame. The electrical connection includes a wire bond formed on the bond pad, a wire lead and a wire bond formed on the lead frame. An encapsulating material protects and insulates the die, and the die is mounted in a package having external pins for interconnecting the electrical circuitry on the die, via the wire bonds, to the outside world.
Packaged devices are typically inserted into sockets on automated test equipment to perform various functional and performance tests prior to delivery to a customer. One example of a test performed on a packaged die is commonly referred to as burn-in testing. Burn-in testing involves accelerated stressing of the parts by subjecting the device to stress level operating conditions for the purpose of accelerating early failures that may occur when the device is assembled in a product. Burn-in generally involves elevating the temperature of a device beyond normal operating conditions and electrically exercising the device. Of course, other types of test programs may be implemented to verify/establish performance grades and operating characteristics.
In a typical test device, multiple sockets are employed to allow testing of multiple devices in parallel or in sequence. The sockets are mounted to a circuit board through which various electrical signals are provided under the direction of a test program to implement the required tests. Devices under test (DUT) are inserted into the sockets by automatic handling equipment that aligns each DUT with a socket and applies an insertion force to seat the device in the socket.
During the insertion process, it is possible that one or more pins on the DUT may not be aligned sufficiently with the corresponding contact holes in the socket to allow the pin to be properly inserted or seated. In some cases, the pin may become bent, broken, or wedged into the socket. Depending on the particular pin damaged and the nature of the damage, the device may or may not pass the functional test.
When the device is removed from the socket, a damaged pin may remain in the socket. Subsequently, when a different DUT is inserted into the socket, the corresponding pin may not be able to be inserted into the socket as the contact hole is plugged. As a result the pin on the second DUT may itself become damaged.
Often, a broken pin may not be identified until a failure trend is recognized and a subsequent manual inspection is performed to verify functionality of the socket. During the time delay between the problem onset and the troubleshooting, multiple devices may be damaged or the test results associated with the devices may be compromised.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the present invention described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the present invention. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.